An IC is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.
Design engineers design ICs by transforming logical or circuit descriptions of the ICs' components into geometric descriptions, called design layouts. IC design layouts typically include circuit modules (e.g., geometric representations of electronic or circuit IC components) with pins, and interconnect lines (e.g., geometric representations of wiring) that connect the pins of the circuit modules. A net is typically defined as a collection of pins that need to be connected. In this fashion, design layouts often describe the behavioral, architectural, functional, and structural attributes of the IC. To create the design layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts.
ICs are manufactured based on the design layouts using a photolithographic process. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e., photomask) are imaged and defined onto a photosensitive layer coating a substrate. To manufacture an IC, photomasks are created using the IC design layout as a template. The photomasks contain the various geometries (e.g., features) of the IC design layout. The various geometries contained on the photomasks correspond to the various base physical IC elements that comprise functional circuit components such as transistors, interconnect wiring, via pads, as well as other elements that are not functional circuit elements but that are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.
As circuit complexity continues to increase and transistor designs become more advanced and ever smaller in size (i.e., die shrink), multi-patterning photolithographic technologies or processes are more often being used to manufacture ICs. Specifically, multi-patterning is a class of lithographic technologies or processes for manufacturing ICs to enhance feature density. The simplest case of multi-patterning is double patterning, where a conventional lithography process is enhanced to produce double the expected number of features. Multi-patterning photolithographic technologies or processes typically require the use of a plurality of different photomasks to form the geometric representations of the electronic or circuit IC components within the IC design layout. The different photomasks typically have different variations and misalignments such that parameters of the electronic or circuit IC components (e.g., transistors and wires) fabricated with the different photomasks may vary differently (e.g., multimodal variability or a distribution of variability for each mask).
Timing analysis (e.g., statistical static timing analysis (SSTA)) needs to model this variation in parameters of the electronic or circuit IC components caused by the multi-patterning technologies or process in an efficient and effective manner. Most SSTA solutions use a sensitivity-based approach to model the effect of variation on timing. This involves establishing how change in a particular device or interconnect parameter affects a desired property of the integrated circuit. This sensitivity to the parameter, in conjunction with its probability distribution (mean and standard deviation), provides a statistical model describing the probability that a parameter will have a certain effect on a device or interconnect property.
However, multimodal variability is difficult to model using conventional SSTA solutions that rely on single Gaussian distributions. For example, previous solutions have included modeling the variability as a single distribution or as a bimodal distribution. The single distribution solution typically models width/spacing as a single distribution that matches mean and variance but results in pessimistic timing result. The bimodal distribution cannot model equipment variability and variability from different sets of photomasks and thus results in very long model run times and inaccurate results.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.